Advancements in micromachining and other microfabrication techniques and processes have enabled the fabrication of a wide variety of MicroElectroMechanical Systems (MEMS) and devices. These include moving rotors, gears, switches, accelerometers, miniaturized sensors, actuator systems, and other such structures.
One popular approach for forming MEMS devices makes use of a modified wafer known as a Silicon-On-Insulator (SOI) wafer. An SOI wafer is essentially a silicon wafer having a silicon dioxide dielectric layer disposed thereon, and having a thin film of active single-crystalline silicon disposed on the dielectric layer.
FIGS. 1-3 illustrate a conventional method for creating a MEMS structure on an SOI wafer. As shown in FIG. 1, in accordance with this method, a silicon wafer substrate 15 is provided having a silicon dioxide dielectric layer 13 disposed thereon. A layer of active single crystal silicon 11 is disposed over the dielectric layer. The layer of active single-crystal silicon is then masked, patterned and selectively etched to yield the structure shown in FIG. 2, after which the dielectric layer is partially removed by selective chemical etching to release the structure. As shown in FIG. 3, the released MEMS structure 12 has a cantilevered portion 17 formed of Si and an anchor portion 19 formed of SiO2.
The methodology depicted in FIGS. 1-3 suffers from a number of drawbacks, one being its reliance on partial chemical etching to define the anchor structure perimeter. Chemical etch rates can vary considerably from one product lot to another in an SOI fabrication scheme, due, for example, to variations in temperature, in the pH of the etching solution, and in the composition of the dielectric material being etched. In a fabrication scheme which relies on partial chemical etching, these variations in etch rates result in variations in the size of the anchor perimeter of the device. Consequently, in order to account for these variations and to ensure that a perimeter having a desired minimum circumference is achieved, SOI devices are typically designed with anchor perimeters that are significantly larger than would be necessary if etching were more predictable. However, the use of a perimeter that is larger than necessary is undesirable in that it increases the overall die area, and also leads to larger parasitic capacitance between the anchor and the substrate.
There is thus a need in the art for a method for producing a MEMS structure on a substrate, and particularly from an SOI wafer, such that the perimeter of the anchor portion of the structure (and hence the wafer size) can be minimized, is not affected by variations in etch rates, and does not vary significantly from one product batch to another. There is also a need in the art for a means for controlling etching in a process used to define the anchor structure and/or release the MEMS structure. There is further a need in the art for a method for making SOI MEMS devices in which parasitic capacitance is minimized. These and other needs are met by the methodologies and devices disclosed herein and hereinafter described.